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| 8M x 36-Bit EDO-DRAM Module HYM 368035S/GS-60 Advanced Information * * 8 388 608 words by 36-Bit organization in 2 banks Fast access and cycle time 60 ns RAS access time 15 ns CAS access time 104 ns cycle time Hyper page mode (EDO) capability 25 ns cycle time Single + 5 V ( 10 %) supply Low power dissipation max. 7260 mW active CMOS - 132 mW standby TTL - 264 mW standby CAS-before-RAS refresh RAS-only-refresh Hidden-refresh 24 decoupling capacitors mounted on substrate All inputs, outputs and clocks fully TTL compatible 72 pin Single in-Line Memory Module (L-SIM-72-17) with 31.75 mm (1250 mil) height Utilizes 24 4M x 3 DRAM's in 300 mil SOJ packages 2048 refresh cycles / 32 ms Optimized for use in byte-write parity applications Tin-Lead contact pads (HYM 368035S-60) Gold contact pads (HYM 368035GS-60) * * * * * * * * * * * * Semiconductor Group 1 4.96 HYM 368035S/GS-60 8M x 36-Bit EDO-Module The HYM 368035S/GS-60 is a 32 MByte EDO-DRAM module organized as 8 388 608 words by 36Bit in two banks assembled on a 72-pin single-in-line package comprising 24 HYB 5117305BJ 4M x 3 DRAMs in 300 mil wide SOJ-packages mounted together with 24 0.2 F ceramic decoupling capacitors on a PC board. The HYB 5117305BJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 368035S-60 dictates the use of early write cycles. Ordering Information Type HYM 368035S-60 HYM 368035GS-60 Ordering Code Q67100-Q3018 Q67100-Q3019 Package L-SIM-72-17 L-SIM-72-17 Description EDO-DRAM Module (access time 60 ns) EDO-DRAM Module (access time 60 ns) Semiconductor Group 2 HYM 368035S/GS-60 8M x 36-Bit EDO-Module Pin Configuration (top view) Pin Names A0-A10 DQ0-DQ35 CAS0 - CAS3 RAS0 - RAS3 WE Address Inputs for HYM 368035S/GS Data Input/Output Column Address Strobe Row Address Strobe Read/Write Input Power (+ 5 V) Ground Presence Detect Pin No Connection VCC VSS PD N.C. Presence Detect Pins -60 PD0 PD1 PD2 PD3 N.C Vss N.C. N.C. Semiconductor Group 3 HYM 368035S/GS-60 8M x 36-Bit EDO-Module Block Diagram Semiconductor Group 4 HYM 368035S/GS-60 8M x 36-Bit EDO-Module Absolute Maximum Ratings Operation temperature range ......................................................................................... 0 to + 70 C Storage temperature range......................................................................................... - 55 to 125 C Input/output voltage ........................................................................ - 0.5 V to min (VCC + 0.5, 7.0) V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation................................................................................................................... 9.24 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 C, VCC = 5 V 10 % Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) Average VCC supply current (RAS, CAS, address cycling, tRC = tRC min) -60 ns version Standby VCC supply current (RAS = CAS = VIH) Average VCC supply current during RAS only refresh cycles (RAS cycling, CAS = VIH, tRC = tRC min) -60 ns version Symbol Limit Values min. max. 2.4 - 0.5 2.4 - - 80 - 10 Unit Test Condition 1) 1) 1) 1) 1) VIH VIL VOH VOL II(L) IO(L) ICC1 VCC + 0.5 V 0.8 - 0.4 80 10 V V V A A 1) - 1320 48 mA mA 2),3),4) ICC2 ICC3 - - 1320 mA 2),4) Semiconductor Group 5 HYM 368035S/GS-60 8M x 36-Bit EDO-Module DC Characteristics1) (cont'd) Parameter Average VCC supply current during hyper page mode (EDO) (RAS = VIL, CAS, address cycling, tHPC = tHPC min) -60 ns version Standby VCC supply current (RAS = CAS = VCC - 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode (RAS, CAS cycling, tRC = tRC min) -60 ns version Symbol Limit Values min. max. Unit Test Condition ICC4 - 660 24 mA mA 2),3),4) ICC5 ICC6 - 1) - 1320 mA 2),4) Capacitance TA = 0 to 70 C, VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A10, WE) Input capacitance (RAS0 - RAS3) Input capacitance (CAS0 - CAS3) I/O capacitance (DQ0-DQ35) Symbol Limit Values min. max. 180 50 40 25 pF pF pF pF - - - - Unit CI1 CI2 CI3 CIO1 Semiconductor Group 6 HYM 368035S/GS-60 8M x 36-Bit EDO-Module AC Characteristics 5)6) TA = 0 to 70 C, VCC = 5 V 10 %, tT = 2 ns Parameter Symbol Limit Values -60 min. max. Unit Note Common Parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 104 40 60 10 0 10 0 10 14 12 15 60 5 1 - - - 10k 10k - - - - 45 30 - - - 50 32 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 Read Cycle Access time from RAS Access time from CAS Access time from column address Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tAA tRAL tRCS tRCH tRRH tCLZ tOFF - - - 30 0 0 0 0 0 60 15 30 - - - - - 15 ns ns ns ns ns ns ns ns ns 8, 9 8, 9 8,10 11 11 8 12 Semiconductor Group 7 HYM 368035S/GS-60 8M x 36-Bit EDO-Module AC Characteristics (cont'd) 5)6) TA = 0 to 70 C, VCC = 5 V 10 %, tT = 2 ns Parameter Symbol Limit Values -60 min. max. Unit Note Early Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 10 10 0 15 15 0 10 - - - - - - - ns ns ns ns ns ns ns 14 14 13 Hyper Page Mode (EDO) Cycle Hyper page mode (EDO) cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in hyper page mode CAS precharge to RAS Delay tHPC tCP tCPA tCOH tRAS tRHCP 25 10 - 5 60 32 - - 32 - 200k - ns ns ns ns ns ns 7 CAS before RAS Refresh Cycle CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - ns ns ns ns ns Semiconductor Group 8 HYM 368035S/GS-60 8M x 36-Bit EDO-Module Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle. 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA, tCPA . tCAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle. 14) These parameters are referenced to the CAS leading edge. Semiconductor Group 9 HYM 368035S/GS-60 8M x 36-Bit EDO-Module Package Outlines L-SIM-72-17 (Single In-line Module) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 10 Dimensions in mm |
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